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With a completely new type of architecture, Swedish Xelerated Packet Devices hope to capture a large portion of the expanding market for network processors. The architecture guarantees constant wire speed and simplifies programming.
Less than a year after being set up, Swedish Xelerated Packet Devices have introduced their first product, a two-chip network processor. The company claims to be the first in the world to offer a solution for 40 Gbit/s, with guaranteed wire speed irrespective of load and data operation type.
"This is just the beginning. Our architecture is scaleable up to 160 Gbit/s," says Thomas Eklund, responsible for business development at Xelerated.
The main secret is the architecture, which is packet based throughout - in each clock cycle one packet arrives and another one leaves. Packets are processed in a multiple-step pipeline, and a software string follows each packet through the process. The order of the packets never need to change, instead they can be handled in real-time as they arrive. The structure is made up by a large number of identical processing elements, so called packet instruction set computers (Pisc).
The company promises a relatively low clock rate for the chips, which will be made in a standard CMOS process. The first samples will not be available until the second quarter of 2002. However, Xelerated chose to introduce them early to give customers time to incorporate them into future designs. Therefore, the launch also included a compiler, an assembler, a simulator with built-in debugging capability, and an FPGA-based design card.
"This is just the beginning. Our architecture is scaleable up to 160 Gbit/s," says Thomas Eklund, responsible for business development at Xelerated.
The main secret is the architecture, which is packet based throughout - in each clock cycle one packet arrives and another one leaves. Packets are processed in a multiple-step pipeline, and a software string follows each packet through the process. The order of the packets never need to change, instead they can be handled in real-time as they arrive. The structure is made up by a large number of identical processing elements, so called packet instruction set computers (Pisc).
The company promises a relatively low clock rate for the chips, which will be made in a standard CMOS process. The first samples will not be available until the second quarter of 2002. However, Xelerated chose to introduce them early to give customers time to incorporate them into future designs. Therefore, the launch also included a compiler, an assembler, a simulator with built-in debugging capability, and an FPGA-based design card.
Gittan Cedervall
