About / Advertise
Swedish Freehand has launched a new DSP architecture. Whilst its core handles main tasks, common algorithms are executed by parallel hardware, so called accelerators. The interface between the core and the accelerators is one of the company's strengths.
Openness, scalability and low power consumption are three key features of Freehand's newly launched DSP architecture Oscar, which stands for Open and Scalable Architecture.
The concept consists of a DSP core, in the form of an Intellectual Property (IP) design block to be embedded in an Asic, together with several accelerators and development tools. The aim is to offer the most efficient solution for DSP System-on-Chip implementations for communications applications.
"The concept as such is not really new. What we have done is to eliminate unnecessary features from the core, and to make a very handsome interface between the core and the accelerators," Freehand's MD Harald Bergh tells Elektroniktidningen.
The DSP core is appropriately called Micro DSP, as it only includes 45,000 gates. It has four well-defined interfaces which can be connected to accelerators, specialised IP blocks for parallel execution of certain tasks. In the accelerators, common algorithms can be implemented in hardware. Freehand has already developed one accelerator for echo cancellation, and is currently working on two more, one for fast Fourier transform and one for protocol management.
The concept consists of a DSP core, in the form of an Intellectual Property (IP) design block to be embedded in an Asic, together with several accelerators and development tools. The aim is to offer the most efficient solution for DSP System-on-Chip implementations for communications applications.
"The concept as such is not really new. What we have done is to eliminate unnecessary features from the core, and to make a very handsome interface between the core and the accelerators," Freehand's MD Harald Bergh tells Elektroniktidningen.
The DSP core is appropriately called Micro DSP, as it only includes 45,000 gates. It has four well-defined interfaces which can be connected to accelerators, specialised IP blocks for parallel execution of certain tasks. In the accelerators, common algorithms can be implemented in hardware. Freehand has already developed one accelerator for echo cancellation, and is currently working on two more, one for fast Fourier transform and one for protocol management.
Gittan Cedervall
